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CXK77910ATM/AYM -10/12
131,072-word by 9-bit High-Speed Synchronous Static RAM
Description The CXK77910ATM/AYM are high-speed CMOS synchronous static RAMs with common I/O pins, organized as 131,072-word-by-9-bit. These synchronous SRAMs integrate input registers, high speed SRAM and output registers onto a single monolithic IC. All input signals are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. 100MHz operation is obtained from a single 5V power supply. Function There are three possible user transactions with the STRAM -- read operation, write operation and deselect operation. The read operation requires WE = "HIGH" and OE = CE = "LOW" on the positive edge of CLK. The memory location pointed to by the contents of the Address registers is read internally and the contents of the location are captured in the Data-out registers on the next positive edge of CLK. The state of Data-out will reflect the contents of the Data-out registers. The write operation requires CE = WE = "LOW" on the positive edge of CLK. The memory location pointed to by the contents of the Address registers is written with the contents of the Data-in registers. The write operation is entirely self-timed, eliminating critical timing edges. The deselect cycle requires CE = "HIGH" or OE = WE = "HIGH" on the positive edge of CLK. Write operation and internal read operation are disabled during the clock CXK77910ATM 44-pin TSOP(II)(Plastic) CXK77910AYM 44-pin TSOP(II)(Plastic)
cycle. The data outputs are forced to a high impedance state during the next clock cycle. During the deselect cycle by CE = "HIGH", STRAM turns to power down mode. Structure Silicon gate CMOS IC Features * Fast cycle time: (Cycle) (Frequency) CXK77910ATM/AYM-10 10.0ns 100MHz CXK77910ATM/AYM-12 12.5ns 80MHz * Fast clock to data valid CXK77910ATM/AYM-10 5.5ns CXK77910ATM/AYM-12 6.5ns * High speed, low power consumption * Single +5V power supply: 5V 5% * Separate output power supply: 3.15V to 5.25V * Inputs and outputs are TTL compatible (3.3V I/O compatible) * Common data input and output * All inputs and outputs are registered on a single clock edge * Self-timed write cycle * Package line-up: 400mil 44 pin TSOP II with 0.8mm pitch
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93831C52-ST
CXK77910ATM/AYM
Pin Configurations (Top View)
CXK77910ATM NC A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
CXK77910AYM A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8 A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
NC A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC
Pin Description (1) Symbol A0 to A16 I/O0 to I/O8 CLK CE WE OE VCCQ VCC VSS/VSSQ Description Address input Data input/output Clock Chip enable input Write enable input Output enable input Output power supply +5V power supply Ground
Block Diagram
CLK CE WE OE Register CLK A0 Register Decoder Self-Timed Write Logic 128K x 9 RAM A16
CLK Register CLK
Sense Amp Register
I/O0
I/O8
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Register
CLK
CXK77910ATM/AYM
Pin Description (2) CLK (Clock, Positive Edge Triggered) All timing is controlled by the rising or positive edge of CLK. All synchronous input and output signals are registered on the positive edge of CLK with set-up and hold times referenced to that edge. Since only one edge of CLK is referenced, the duty cycle of CLK is not critical. A0 to A16 (Address) The Address inputs are decoded on-chip to select one of 131,072 words. The state of the Address inputs is registered into the Address register on the positive edge of CLK. The Address inputs must be valid during every positive edge with all set-up and hold times referenced to that edge. I/O0 to I/O8 (Data Input/Output) I/O terminals are three-state and data input/output common. The state is defined by the Control block (refer to the truth table on page 4). The data inputs for write operation must be valid during every positive edge of CLK with all set-up and hold times referenced to that edge. The data outputs are triggered by the positive edge of CLK and the contents of the Output-Registers are presented. WE (Synchronous Write Enable, Active Low) WE is used to indicate whether a read or write operation is to be performed. WE is "LOW" to perform a write operation. WE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. The internal timing required to store data into the memory array is self-timed. CE (Synchronous Chip Enable, Active Low) CE is used to select the Synchronous SRAM when low (or deselect when high). When selected, the Synchronous SRAM will perform a read or write operation (refer to the truth table on page 4). The state of CE is registered on every positive edge of CLK with set-up and hold times referenced to that edge.
OE (Synchronous Output Enable, Active Low) OE is used to indicate that a read operation is to be performed. If the Synchronous SRAM is selected, the OE is low to perform a read operation (refer to the truth table on page 4). The state of OE is registered on every positive edge of CLK with set-up and hold times referenced to that edge.
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CXK77910ATM/AYM
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature * time Symbol VCC VIN VO PD Topr Tstg Tsolder
(Ta = +25C, GND = 0V) Rating -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 1 0 to 70 -55 to +150 235 * 10 Unit V V V W C C C * sec
Truth Table CLK CE (tn) H L L L WE (tn) H H L OE (tn) H L Mode Deselect Read Read Write Hi-Z Hi-Z Data out* Data in I/O to 8 VCC Current ISB ICC ICC ICC
: "H" or "L" *Data come out on the next positive edge of CLK.
DC Recommended Operating Conditions Item Supply voltage Output supply voltage Input high voltage Input low voltage Symbol VCC VCCQ VIH VIL Min. 4.75 3.15 2.2 -0.3* Typ. 5.0 -- -- --
(Ta = +25C, GND = 0V) Max. 5.25 5.25 VCC +0.3 0.8 Unit V V V V
*VIL = -3.0V min. for pulse width less than 20ns.
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CXK77910ATM/AYM
Electrical Characteristics DC and Operating Characteristics Item Input leakage current Output leakage current Average operating current Standby current Output high voltage Output low voltage Symbol ILI ILO ICC ISB VOH VOL Test conditions VIN = GND to VCC Vo = GND to VCC OE = VIH Duty = 100% IOUT = 0mA CE VIH Cycle = Min. Duty = 100% IOH = -2.0mA IOL = 4.0mA (VCC = 5V 5%, GND = 0V, Ta = 0 to +70C) Min. -1 -1 -- -- 2.4 -- Max. 1 A 1 150 mA 130 -- 0.4 V Unit
I/O Capacitance Item Input capacitance I/O capacitance Symbol CIN CI/O Test Conditions VIN = 0V VI/O = 0V
(Ta = +25C, f = 1MHz) Min. -- -- Max. 5 7 Unit pF pF
Note) These parameters are sampled and are not 100% tested.
AC Characteristics * AC Test Conditions Item Input pulse high level Input pulse low level Input rise time Input fall time
Output Load (1) (VCC = 5V 5%, Ta = 0 to +70C) Conditions VIH = 3.0V VIL = 0V tr = 3ns tf = 3ns 1.5V Fig. 1
I/O
Output Load (2) *2
5V 480
I/O 50pF*1 50pF*1
255
Input/output reference level Output load conditions
*1. Including scope and jig capacitance. *2. For tCKHQZ, tCKHQX.
Fig. 1
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CXK77910ATM/AYM
* Read Cycle (WE = "H") -10 Item Read cycle time Clock high pulse width Clock low pulse width Clock to data valid Address setup to clock high Address hold from clock high Chip enable setup to clock high Chip enable hold from clock high Output enable setup to clock high Output enable hold from clock high Clock high to output low-Z Clock high to output high-Z Symbol tCKHCKH tCKHCKL tCKLCKH tCKHQV tAVCKH tCKHAX tCEVCKH tCKHCEX tOEVCKH tCKHOEX tCKHQX* tCKHQZ* Min. 10 3.5 3.5 -- 2.5 0.5 2.5 0.5 2.5 0.5 1.5 -- Max. -- -- -- 5.5 -- -- -- -- -- -- -- 4.5 Min. 12.5 4 4 -- 2.5 0.5 2.5 0.5 2.5 0.5 1.5 -- -12 Max. -- -- -- 6.5 -- -- -- -- -- -- -- 5 ns Unit
*Transition is measured 200mV from steady voltage with specfified loading in Fig. 1-(2). This parameter is sampled and is not 100% tested.
* Write Cycle -10 Item Write cycle time Clock high pulse width Clock low pulse width Address setup to clock high Address hold from clock high Chip enable setup to clock high Chip enable hold from clock high Write enable setup to clock high Write enable hold from clock high Input data setup to clock high Input data hold from clock high Symbol tCKHCKH tCKHCKL tCKLCKH tAVCKH tCKHAX tCEVCKH tCKHCEX tWEVCKH tCKHWEX tDVCKH tCKHDX Min. 10 3.5 3.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 Max. -- -- -- -- -- -- -- -- -- -- -- Min. 12.5 4 4 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 -12 Max. -- -- -- -- -- -- -- -- -- -- -- ns Unit
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CXK77910ATM/AYM
Timing Waveform * Read Cycle
CLK tCKHCKH tAVCKH tCKHAX Address n n+1 n+2 tCKHCKL tCKLCKH
WE
tWEVCKH tCKHWEX CE tCEVCKH tCKHCEX
OE tOEVCKH tCKHOEX tCKHQV Data Out Qn - 2* Qn - 1* Qn*
*Valid data from CLK high is the data from the previous cycle
* Write Cycle: OE = VIH or VIL
CLK tCKHCKH tAVCKH tCKHAX Address n n+1 n+2 tCKHCKL tCKLCKH
tCEVCKH tCKHCEX CE
tWEVCKH tCKHWEX WE
tOECKH tCKHOEX OE
tDVCKH tCKHDX Data In Dn D+1 Dn + 2
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CXK77910ATM/AYM
* Read/Write Cycle
CLK tCKHCKH tAVCKH tCKHAX Address n n+1 n+2 tCKHCKL tCKLCKH
tCEVCKH tCKHCEX CE
tWEVCKH tCKHWEX WE
tOEVCKH tCKHCEX OE
tDVCKH tCKHDX I/O Qn-2 tCKHQZ Dn
tCKHQX
Qn + 1 tCKHQV
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CXK77910ATM/AYM
Example of Representative Characteristics
Supply Current vs. Supply Voltage
1.4 1.4
Supply Current vs. Ambient Temperature
ICC -- Supply Current (Normalized)
1.2
ICC -- Supply Current (Normalized)
1.2
ICC 1.0
ICC 1.0
0.8 Ta = +25C
0.8 VCCAA5.0V
0.6 4.5
0.6 4.75 5.0 5.25 VCC -- Supply Voltage [V] 5.5 0 20 40 60 Ta -- Ambient Temperature [C] 80
Supply Current vs. Frequency
1.0 1.4
Access Time vs. Load Capacitance
0.8 Read, Write
tCKHQV -- Access Time (Normalized)
ICC -- Supply Current (Normalized)
1.2
0.6
1.0
0.4
VCC = 5.0V Ta = +25C
0.8
VCC = 5.0V Ta = +25C
0.2 0 20 40 60 Frequency (1/tCKHCKH) [MHz] 80
0.6 0 25 50 75 CL -- Load Capacitance [pF] 100
Cycle Time (Minimum)/Access Time vs. Supply Voltage
1.4 1.4
Cycle Time (Minimum)/Access Time vs. Ambient Temperature
tCKHCKH -- Cycle Time, tCKHQV -- Access Time (Normalized)
tCKHCKH -- Cycle Time, tCKHQV -- Access Time (Normalized)
1.2
1.2
tCKHQV 1.0 tCKHCKH
tCKHCKH 1.0 tCKHQV
0.8 Ta = +25C
0.8 VCC = 5.0V
0.6 4.5
0.6 4.75 5.0 5.25 VCC -- Supply Voltage [V] 5.5 0 20 40 60 Ta -- Ambient Temperature [C] 80
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CXK77910ATM/AYM
Standby Current vs. Supply Voltage
1.4
Standby Current vs. Ambient Temperature
1.8
ISB -- Standby Current (Normalized)
1.2
ISB -- Standby Current (Normalized)
1.4
ISB 1.0
1.0
0.8 Ta = +25C
0.6 VCC = 5.0V
0.6 4.5
0.2 4.75 5.0 5.25 VCC -- Supply Voltage [V] 5.5 0 20 40 60 Ta -- Ambient Temperature [C] 80
Input Voltage Level vs. Supply Voltage
1.4
Input Voltage Level vs. Ambient Temperature
1.4
1.2
VIIL, VIIH -- Input Voltage (Normalized)
VIL, VIH -- Input Voltage (Normalized)
1.2
1.0
VIL,VIH
1.0 VIIL,VIIH
0.8 Ta = +25C
0.8 VCC = 5.0V
0.6 4.5
0.6 4.75 5.0 5.25 VCC -- Supply Voltage [V] 5.5 0 20 40 60 Ta -- Ambient Temperature [C] 80
Output Low Current vs. Output Low Voltage
1.8
Output High Current vs. Output High Voltage
4
IOH -- Output High Current (Normalized)
IOL -- Output Low Current (Normalized)
VCC = 5.0V Ta = +25C 3
1.4
1.0
2
0.6
VCC = 5.0V Ta = +25C
1
0.2 0 0.2 0.4 0.6 VOL -- Output Low Voltage [V] 0.8
0 0 1 2 3 VOH -- Output High Voltage [V] 4
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CXK77910ATM/AYM
Package Outline CXK77910ATM
Unit : mm
44PI TSO P( I ( N I ) PLASTI )400m i C l
1. AX 2M 18. 41}0. 1 0. 1 44 23
10. 16}0. 1
76}0. 2 11.
A
1 0. 8 B 0. 3}0. 1
22 0. 13 M
{0. 05 125 0. |0. 02
{0. 1 0. 1|0. 05
0. 32}0. 08 ( 3) 0.
145}0. 055 0.
0. ( 125)
0K t 10K o D ETAI A L D ETAI B L N O TED i m ensi on g hdoes
PAC KAG E STR U C TU R E PAC KAG E M ATER I AL SO N Y C O D E EI C O D E AJ JED EC C O D E TSO P( I I ) 44PL01 TSO P( I 044- 0400I) PA LEAD TR EATM EN T LEAD M ATER I AL PAC KAG E W EI H T G EPO XY R ESI N SO LD ER PLATI G N 42 ALLO Y 0. 5g
noti ude m ol pr r on. ncl d otusi
CXK77910AYM
44PI TSO P( I ( N I ) PLASTI )400m i C l
1. AX 2M * 41}0. 1 18. 1 0. 1 22
10. * 16}0. 1
76}0. 2 11.
A
44 0. 8 0. 3}0. 1
23 0. 13 M
{0. 05 125 0. |0. 02
B {0. 1 0. 1|0. 05
0. 32}0. 08
0. ( 125)
( 3) 0.
145}0. 055 0.
0Kt o 10K D ETAI A L
D ETAI B L N O TED i m ensi g on hdoes not i ude m ol pr r on. ncl d otusi
PAC KAG E STR U C TU R E
PAC KAG E M ATER I AL SO N Y C O D E EI C O D E AJ JED EC C O D E TSO P( I I ) 44PL01R TSO P( I 044- 0400I) PB LEAD TR EATM EN T LEAD M ATER I AL PAC KAG E W EI H T G EPO XY R ESI N SO LD ER PLATI G N 42 ALLO Y 0. 5g
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5}0. 1 0.
5}0. 1 0.

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